14nm finfet simulation project

the following is the 14nm finfet simulation in lam research's coventor semulator3d software i did for. my ee222 final project. this is the first and only grad class i've taken thus far, so enjoy. there are several problems with the simulation, such as:

probably incorrect dimensions because it was thought (and not quite clarified) that 14nm is just a name and not the real gate pitches of the device. so much for marketing
not so hot simulation for the p-type transistor
not enough gates, since normally these devives have around 3 gates per mosfet
unadjusted bandgap energy for materials e.g. the TiN, TaN, HfO2
calculations that are wildly different from the simulation, with the simulation being more akin to the actual behavior

anyways, enjoy!